The present invention relates to testing of integrated circuits and particularly to a method of producing test vectors in response to circuit design information.
As a result of the complexity of very large scale integrated circuits devices, and the inaccessibility of internal conductive paths in the finished product, efforts are frequently made at the design stage to ascertain the testability of a proposed circuit, and to design usable sets of test inputs or vectors which will check for possible faults in the manufactured device. The design vectors, i.e., those vectors which are normally intended for the circuit normal operations, may or may not be appropriate for uncovering hidden faults in the circuit, and these faults may become apparent only under unusual operating conditions. If the number of circuit input terminals is large, applying all combinations of binary input values thereto for the purpose of uncovering faults would become impractical. An alternative method utilizes an automatic test pattern generator for supplying an input vector suitable for uncovering some designated fault or faults, such as "stuck-at" faults within the circuit. Then, a fault simulator procedure is employed for checking results and ascertaining whether certain other faults will also be detected using the same input vector. That is, the fault simulator tries to grade the effectiveness of a given test. Then, another fault is proposed to the automatic test pattern generator, which fault was not covered by the first test vector, and the automatic test pattern generator provides a second test vector. This iterative process continues until a desired or acceptable number of faults are covered. Unfortunately, these procedures are very lengthy and expensive in terms of the computer time required for simulation. Consequently many designers avoid test methods of this type where possible.
In general, it does not appear there has heretofore been a really satisfactory method of generating test vectors to be employed with integrated circuit devices.